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rev. 0 ad1833a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. multichannel, 24-bit, 192 khz, - dac features 5 v stereo audio system with 3.3 v tolerant digital interface supports 96 khz sample rates on 6 channels and 192 khz on 2 channels supports 16-/20-/24-bit word lengths multibit - modulators with perfect differential linearity restoration for reduced idle tones and noise floor data directed scrambling dacs?east sensitive to jitter differential output for optimum performance dacs signal-to-noise and dynamic range: 110 db ?4 db thd + n?-channel mode ?5 db thd + n?-channel mode on-chip volume control per channel with 1024-step linear scale software controllable clickless mute digital de-emphasis processing supports 256 f s , 512 f s , and 768 f s master clock modes power-down mode plus soft power-down mode flexible serial data port with right-justified, le ft- justified, i 2 s compatible, and dsp seria l port modes supports packed data mode and tdm mode 48-lead lqfp plastic package applications dvd video and audio players home theater systems automotive audio systems set-top boxes digital audio effects processors functional block diagram agnd dgnd filtr filtd mclk cdata clatch cclk outlp1 outln1 outlp2 outln2 outlp3 outln3 outrp3 outrn3 outrp2 outrn2 outrp1 outrn1 zero flags dv dd1 dv dd2 av dd reset sout ad1833a spi port data port l/rclk bclk sdin1 sdin2 sdin3 interpolator dac interpolator dac interpolator dac interpolator dac interpolator dac filter engine interpolator dac general description the ad1833a is a complete, high performance, single-chip, multichannel, digital audio playback system. it features six audio playback channels, each comprising a high performance digital interpolation filter, a multibit s - d modulator featuring analog devices?patented technology, and a continuous-time voltage-out analog dac section. other features include an on-chip clickless attenuator and mute capability for each channel, programmed through an spi compatible serial control port. the ad1833a is fully compatible with all known dvd formats, accommodating word lengths of up to 24 bits at sample rates of 48 khz and 96 khz on all six channels while supporting a 192 khz sample rate on two channels. it also provides the redbook stan- dard 50 m s/15 m s digital de-emphasis filters at sample rates of 32 khz, 44.1 khz, and 48 khz. the ad1833a has a very flexible serial data input port that allows glueless interconnection to a variety of adcs, dsp chips, aes/ebu receivers, and sample rate converters. it can be con- figured in right-justified, left-justified, i 2 s, or dsp serial port compatible modes. the ad1833a accepts serial audio data in msb first, twos complement format. the ad1833a can be operated from a single 5 v power supply; it also features a separate supply pin for its digital interface that allows it to be interfaced to devices using 3.3 v power supplies. the ad1833a is fabricated on a single monolithic integrated circuit and is housed in a 48-lead lqfp package for operation from ?0 c to +85 c.
rev. 0 ? ad1833a?pecifications parameter min typ max unit test conditions analog performance digital-to-analog converters dynamic range (20 hz to 20 khz, ?0 dbfs input) with a-weighted filter ad1833aa 106.5 110.0 db ad1833aa 110.5 db f s = 96 khz ad1833ac 107.0 db total harmonic distortion + noise ?5 ?9 db two channels active ?4 db six channels active ?5 db 96 khz, two channels active ?4 db 96 khz, six channels active snr 110 db interchannel isolation 108 db dc accuracy gain error 3% interchannel gain mismatch 0.2 % gain drift 80 ppm/ c interchannel crosstalk (eiaj method) ?20 db interchannel phase deviation 0.1 degrees volume control step size (1023 linear steps) 0.098 % volume control range (max attenuation) +63.5 (0.098) db (%) mute attenuation ?3.5 (0.098) db (%) de-emphasis gain error 0.1 db full-scale output voltage at each pin (single-ended) 1 (2.8) v rms (v p-p) output resistance measured differentially 150 w common-mode output volts 2.2 v dac interpolation filter? mode (48 khz) pass band 21.768 khz pass-band ripple 0.01 db stop band 24 khz stop-band attenuation 70 db group delay 510 m s dac interpolation filter? mode (96 khz) pass band 37.7 khz pass-band ripple 0.03 db stop band 55.034 khz stop-band attenuation 70 db group delay 160 m s dac interpolation filter? mode (192 khz) pass band 89.954 khz pass-band ripple 1db stop band 104.85 khz stop-band attenuation 70 db group delay 140 m s test conditions, unless otherwise noted * supply voltages (av dd , dv ddx )5 v ambient temperature 25 c input clock 12.288 mhz, (8 mode) input signal nominally 1 khz, 0 dbfs (full-scale) input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance 100 pf load impedance 10 k w * performance is identical for all channels (except for the interchannel gain mismatch and interchannel phase deviation specifications).
rev. 0 ? ad1833a parameter min typ max unit test conditions digital i/o input voltage hi 2.4 v input voltage lo 0.8 v output voltage hi dv dd2 0.4 v output voltage lo 0.4 v power supplies supply voltage (av dd and dv dd1 ) 4.5 5 5.5 v supply voltage (dv dd2 ) 3.3 dv dd1 v supply current i analog 38.5 42 ma supply current i digital 42 48 ma active 2m a power-down power supply rejection ratio 1 khz 300 mv p-p signal at analog supply pins ?0 db 20 khz 300 mv p-p signal at analog supply pins ?0 db specifications subject to change without notice. digital timing parameter min max unit comments master clock and reset t ml mclk lo (all modes) * 15 ns 24 mhz clock, clock doubler bypassed t mh mclk hi (all modes) * 15 ns 24 mhz clock, clock doubler bypassed t pdr pd / rst lo 20 ns spi port t cch cclk hi pulsewidth 20 ns t ccl cclk lo pulsewidth 20 ns t ccp cclk period 80 ns t cds cdata setup time 10 ns to cclk rising t cdh cdata hold time 10 ns from cclk rising t cls clatch setup 10 ns to cclk rising t clh clatch hold 10 ns from cclk rising dac serial port t dbh bclk hi 15 ns t dbl bclk lo 15 ns t dls l/rclk setup 10 ns to bclk rising t dlh l/rclk hold 10 ns from bclk rising t dds sdata setup 10 ns to bclk rising t ddh sdata hold 15 ns from bclk rising tdm mode master t tmbd bclktdm delay 20 ns from mclk rising t tmfsd fstdm delay 10 ns from bclktdm rising t tmdds sdin1 setup 15 ns to bclktdm falling t tmddh sdin1 hold 15 ns from bclktdm falling tdm mode slave f tsb bclktdm frequency 256 f s t tsbch bclktdm high 20 ns t tsbcl bclktdm low 20 ns t tsfs fstdm setup 10 ns to bclktdm falling t tsfh fstdm hold 10 ns from bclktdm falling t tsdds sdin1 setup 15 ns to bclktdm falling t tsddh sdin1 hold 15 ns from bclktdm falling auxiliary interface t axlrd l/rclk delay 10 ns from bclk falling t axdd data delay 10 ns from bclk falling t axbd auxbclk delay 20 ns from mclk rising * mclk symmetry must be better than 60:40 or 40:60. specifications subject to change without notice. (guaranteed over ?0 c to +85 c, av dd = dv dd = 5 v 10%)
rev. 0 ? ad1833a mclk t mh pd/rst t ml t pdr figure 1. mclk and reset timing clatch cclk cin d0 d15 d14 d8 t cch t ccl d9 t cds t cdh t cls t clh t ccp figure 2. spi port timing bclk l/rclk sdata lef t-justified mode sdata right-ju stified mode lsb sdata i 2 s mode msb msb-1 msb msb t dbh t dbl t dls t dds t ddh t dds t dlh t ddh t dds t dds t ddh t ddh figure 3. serial port timing msb t tmbd t tmfsd t tmdds t tmddh mclk bclktdm fstdm sdin1 t tsbcl t tsbch t tsddh t tsdds t tsfs t tsfh figure 4. tdm master and slave mode timing
rev. 0 ad1833a ? absolute maximum ratings * (t a = 25 c, unless otherwise noted.) av dd , dv ddx to agnd, dgnd . . . . . . . . ?.3 v to +6.5 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v digital i/o voltage to dgnd . . . . . ?.3 v to dv dd2 + 0.3 v analog i/o voltage to agnd . . . . . . ?.3 v to av dd + 0.3 v operating temperature range industrial (a version) . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c lqfp, q ja thermal impedance . . . . . . . . . . . . . . . . . 91 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. msb mclk aux bclk auxl / r clk aux data t axdd t axlrd t axbd figure 5. auxiliary interface timing ordering guide model temperature range package description package option ad1833aast ?0 c to +85 c low profile quad flat package st-48 ad1833acst ?0 c to +85 c low profile quad flat package st-48 eval-ad1833aeb evaluation board AD1833AAST-REEL ?0 c to +85 c low profile quad flat package st-48 ad1833acst-reel ?0 c to +85 c low profile quad flat package st-48 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1833a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. 0 ad1833a ? pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) outrp1 outrn1 av dd av dd agnd agnd agnd outlp1 outln1 av dd av dd agnd agnd agnd dgnd dv dd1 zeroa zero3r dgnd dv dd2 reset zero1l ad1833a zero3l zero1r outln2 outlp2 outln3 outlp3 av dd filtd filtr agnd outrp3 outrn3 outrp2 outrn2 zero2r clatch cdata cclk l/rclk bclk mclk sdin1 sdin2 sdin3 sout zero2l pin function descriptions pin no. mnemonic in/out description 1 outlp1 o dac 1 left channel positive output. 2 outln1 o dac 1 left channel negative output. 3, 4, 33, 34, 44 av dd analog supply. 5, 6, 7, 30, 31, 32, 41 agnd analog ground. 8, 29 dgnd digital ground. 9dv dd1 digital supply to core logic. 10 zeroa o flag to indicate zero input on all channels. 11 zero3r o flag to indicate zero input on channel 3 right. 12 zero3l o flag to indicate zero input on channel 3 left. 13 zero2r o flag to indicate zero input on channel 2 right. 14 clatch i latch input for control data (spi port). 15 cdata i serial control data input (spi port). 16 cclk i clock input for control data (spi port). 17 l/rclk i/o left/right cl ock for dac data input; fstdm input in tdm slave mode; fstdm output in tdm master mode. 18 bclk i/o bit clock for dac data input; bclktdm input in tdm slave mode; bclktdm output in tdm master mode. 19 mclk i master clock input. 20 sd in 1i data input for channel 1 left/right (data stream input in tdm and packed modes). 21 sdin2 i/o data input for channel 2 left/right (l/rclk output to auxiliary dac in tdm mode). 22 sd in 3 i/o data input for channel 3 left/right (bclk output to auxiliary dac in tdm mode). 23 sout o auxiliary i 2 s output (available in tdm mode). 24 zero2l o flag to indicate zero input on channel 2 left. 25 zero1r o flag to indicate zero input on channel 1 right. 26 zero1l o flag to indicate zero input on channel 1 left. 27 reset ip ower-down and reset control. 28 dv dd2 power supply to output interface logic. 35 outrn1 o dac 1 right channel negative output. 36 outrp1 o dac 1 right channel positive output. 37 outrn2 o dac 2 right channel negative output. 38 outrp2 o dac 2 right channel positive output. 39 outrn3 o dac 3 right channel negative output.
rev. 0 ad1833a ? definition of terms dynamic range the ratio of a full-scale input signal to the integrated input noise in the pass band (20 hz to 20 khz), expressed in decibels. dynamic range is measured with a ?0 db input signal and is equal to (s/[thd + n]) +60 db. note that spurious harmonics are below the noise with a ?0 db input, so the noise level establishes the dynamic range. the dynamic range is specified with and without an a-weight filter applied. signal to (total harmonic distortion + noise) [s/(thd + n)] the ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. pass band the region of the frequency spectrum unaffected by the attenuation of the digital decimator? filter. pass-band ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. stop band the region of the frequency spectrum attenuated by the digital decimator? filter to the degree specified by stop-band attenuation. gain error with a near full-scale input, the ratio of actual output to expected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a nearly full-scale input with a change in temperature, expressed as parts-per-million (ppm/ c). crosstalk (eiaj method) ratio of response on one channel with a grounded input to a full-scale 1 khz sine wave input on the other channel, expressed in decibels. power supply rejection with no analog input, signal present at the output when a 300 mv p-p signal is applied to the power supply pins, expressed in decibels of full scale. group delay intuitively, the time interval required for an input pulse to appear at the converter? output, expressed in ms. more precisely, the derivative of radian phase with respect to the radian frequency at a given frequency. group delay variation the difference in group delays at different input frequencies. specified as the difference between the largest and the smallest group delays in the pass band, expressed in m s. pin function descriptions (continued) pin no. mnemonic in/out description 40 outrp3 o dac 3 right channel positive output. 42 filtr reference/filter capacitor connection. recommend 0.1 m f/10 m f decouple to analog ground. 43 filtd filter capacitor connection. recommend 0.1 m f/10 m f decouple to analog ground. 45 outlp3 o dac 3 left channel positive output. 46 outln3 o dac 3 left channel negative output. 47 outlp2 o dac 2 left channel positive output. 48 outln2 o dac 2 left channel negative output.
rev. 0 ad1833a ? 0.010 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.008 0.006 0.004 0.002 0 ?.002 ?.004 ?.006 ?.008 ?.010 db hz 10 4 tpc 1. pass-band response, 8 mode 10 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 0 ?0 ?0 ?0 db hz 10 4 ?0 ?0 ?0 ?0 ?0 ?0 ?00 tpc 2. transition band response, 8 mode 0 0.5 1.5 2.0 2.5 3.0 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 db hz 10 5 1.0 tpc 3. complete response, 8 mode ?ypical performance characteristics 0.10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.08 0.06 0.04 0.02 0 ?.02 ?.04 ?.06 ?.08 ?.10 db hz 10 4 tpc 4. pass-band response, 4 mode 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 db hz 10 4 tpc 5. 40 khz pass-band response, 4 mode 10 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 0 ?0 ?0 ?0 db hz 10 4 ?0 ?0 ?0 ?0 ?0 ?0 ?00 tpc 6. transition band response, 4 mode
rev. 0 ad1833a ? 0 0.5 1.5 2.0 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 db hz 10 5 1.0 2.5 3.0 tpc 7. complete response, 4 mode 2.0 0 12345678 1.5 0.5 0 ?.5 ?.0 ?.5 ?.0 db hz 10 4 1.0 tpc 8. 80 khz pass-band response, 2 mode 10 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 0 ?0 ?0 ?0 db hz 10 5 ?0 ?0 ?0 ?0 ?0 ?0 ?00 tpc 9. transition band response, 2 mode 0 0.5 1.5 2.0 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 db hz 10 5 1.0 tpc 10. complete response, 2 mode
rev. 0 ad1833a ?0 functional description device architecture the ad1833a is a six-channel audio dac featuring multibit sigma-delta ( s - d ) technology. the ad1833a features three stereo converters (providing six channels); each stereo channel is con- trolled by a common bit-clock (bclk) and synchronization signal (l/rclk). general overview the ad1833a is designed to run with an internal mclk (imclk) of 24.576 mhz and a modulator rate of 6.144 mhz (i.e., imclk/4). from this imclk frequency, sample rates of 48 khz and 96 khz can be achieved on six channels or 192 khz can be achieved on two channels. the internal clock should never be run at a higher frequency but may be reduced to achieve lower sampling rates, i.e., for a sample rate of 44.1 khz, the appro- priate internal mclk is 22.5792 mhz. the modulator rate scales in proportion with the mclk scaling. interpolator the interpolator consists of as many as three stages of sample rate doubling and half-band filtering followed by a 16-sample zero order hold (zoh). the sample rate doubling is achieved by zero stuffing the input samples, and a digital half-band filter is used to remove any images above the band of interest and to bring the zero samples to their correct values. the interpolator output must always be at a rate of imclk/64. depending on the interpolation rates selected, one, two, or all three stages of doubling may be switched in. this allows for three different sample rate inputs for any given imclk. for an imclk of 24.576 mhz, all three doubling stages are used with a 48 khz input sample rate; with a 96 khz input sample rate, only two doubling stages are used; and with a 192 khz input sample rate, only one doubling stage is used. in each case, the input sample frequency is increased to 384 khz (imclk/64). the zoh holds the interpolator samples for upsampling by the modulator. this is done at a rate 16 times the interpolator output sample rate. modulator the modulator is a 6-bit, second order implementation and uses data scrambling techniques to achieve perfect linearity. the modu- lator sam ples the output of the interpolator stage(s) at a rate of (imclk/4). operating features spi register definitions the spi port allows flexible control of the device? programmable functions. it is organized around nine registers: six individual channel volume registers and three control registers. each write operation to the ad1833a spi control port requires 16 bits of serial data in msb-first format. the four most significant bits are used to select one of nine registers (seven register addresses are reserved), and the bottom 10 bits are written to that register. this allows a write to one of the nine registers in a single 16-bit transaction. the spi cclk signal is used to clock in the data. the incoming data should change on the falling edge of this signal and remain valid during the rising edge. at the end of the 16 cclk periods, the clatch signal should rise to latch the data internally into the ad1833a (see figure 2). the serial interface format used on the control port uses a 16-bit serial word, as shown in table i. the 16-bit word is divided into several fields: bits 15 through 12 define the register address, bits 11 and 10 are reserved and must be programmed to 0, and bits 9 through 0 are the data field (which has specific definitions, depending on the register selected). table i. control port map register address reserved 1 data field 15 2 14 13 12 11 10 9876543210 notes 1 must be programmed to zero. 2 bit 15 = msb. bit 15 bit 14 bit 13 bit 12 register function 00 00 dac control 1 00 01 dac control 2 00 10 dac volume 1 00 11 dac volume 2 01 00 dac volume 3 01 01 dac volume 4 01 10 dac volume 5 01 11 dac volume 6 10 00 dac control 3 10 01 reserved 10 10 reserved 10 11 reserved 11 00 reserved 11 01 reserved 11 10 reserved 11 11 reserved
rev. 0 ad1833a ?1 dac word width the ad1833a will accept input data in three separate word- lengths?6 bits, 20 bits, and 24 bits. the word length may be selected by writing to control bits 4 and 3 in dac control register 1 (see table v). table v. word length settings bit 4 bit 3 word length 00 24 bits 01 20 bits 10 16 bits 11 reserved power-down control the ad1833a can be powered down by writing to control bit 2 in dac control register 1 (see table vi). table vi. power-down control bit 2 power-down setting 0n ormal operation 1 power-down mode interpolator mode the ad1833a? dac interpolators can be operated in one of three modes? , 4 , or 2 ?then correspond to 48 khz, 96 khz, and 192 khz modes, respectively (for imclk = 24.576 mhz). the interpolator mode may be selected by writing to control bits 1 and 0 in dac control register 1 (see table vii). table vii. interpolator mode settings bit 1 bit 0 interpolator mode 00 8x (48 khz) * 01 2x (192 khz) * 10 4x (96 khz) * 11 reserved * for imclk = 24.576 mhz. dac control register 1 de-emphasis the ad1833a has a built-in de-emphasis filter that can be used to decode cds that have been encoded with the standard red book 50 m s/15 m s emphasis response curve. three curves are available, one each for 32 khz, 44.1 khz, and 48 khz sampling rates. the filters may be selected by writing to control bits 9 and 8 in dac control register 1 (see table iii). table iii. de-emphasis settings bit 9 bit 8 de-emphasis 00 disabled 01 44.1 khz 10 32 khz 11 48 khz data serial interface mode the ad1833a? serial data interface is designed to accept data in a wide range of popular formats including i 2 s, right-justified (rj), left-justified (lj), and flexible dsp modes. the l/rclk pin acts as the word clock (or frame sync) to indicate sample interval boundaries. the bclk defines the serial data rate while the data is input on the sdin1?din3 pins. the serial mode settings may be selected by writing to control bits 7 through 5 in the dac control register 1 (see table iv). table iv. data serial interface mode settings bit 7 bit 6 bit 5 serial mode 0 00i 2 s 0 01r ight justify 0 10 dsp 0 11l eft justify 1 00p acked mode 1 (256) 1 01p acked mode 2 (128) 1 10 tdm mode 1 11r eserved table ii. dac control register 1 function data-word power-down interpolator address reserved 1 de-emphasis serial mode width reset mode 15?2 11 10 9? 7? 4? 2 1? 0000 0 0 00 = none 000 = i 2 s 00 = 24 bits 0 = normal 00 = 8 (48 khz) 2 01 = 44.1 khz 001 = rj 01 = 20 bits 1 = pwrdwn 01 = 2 (192 khz) 2 10 = 32.0 khz 010 = dsp 10 = 16 bits 10 = 4 (96 khz) 2 11 = 48.0 khz 011 = lj 11 = reserved 11 = reserved 100 = pack mode 1 (256) 101 = pack mode 2 (128) 110 = tdm mode 111 = reserved notes 1 must be programmed to zero. 2 for imclk = 24.576 mhz.
rev. 0 ad1833a ?2 table x. dac control register 3 function stereo replicate address reserved * reserved * (192 khz) mclk select zero detect reserved * tdm mode 15?2 11 10 9? 5 4? 2 1 0 1000 0 0 0 0 = normal 00 = imclk = mclk 2 0 = active high 0 0 = master 1 = replicate 01 = imclk = mclk 1 1 = active low 1 = slave 10 = imclk = mclk 2 / 3 * must be programmed to zero. dac control register 2 dac control register 2 contains individual channel mute controls for each of the six dacs. default operation (bit = 0) is muting off. bits 9 through 6 of control register 2 are reserved and should be programmed to zero (see table viii). dac control register 3 stereo replicate the ad1833a allows the stereo information on channel 1 (sdin1?eft 1 and right 1) to be copied to channels 2 and 3 (left/right 2 and left/right 3). these signals can be used in an external summing amplifier to increase potential signal snr. stereo replicate mode can be enabled by writing to control bit 5 (see table xi). note that replication is not reflected in the zero flag status. table xi. stereo replicate bit 5 stereo mode 0n ormal 1c hannel 1 data replicated on channels 2 and 3 table viii. dac control register 2 function address reserved * reserved * mute control 15?2 11 10 9? 5 4 3 2 1 0 0001 0 0 0 channel 6 channel 5 channel 4 channel 3 channel 2 channel 1 0 = mute off 0 = mute off 0 = mute off 0 = mute off 0 = mute off 0 = mute off 1 = mute on 1 = mute on 1 = mute on 1 = mute on 1 = mute on 1 = mute on * must be programmed to zero. table ix. muting control bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 muting xxxxx1 m ute channel 1 xxxx1 x m ute channel 2 xxx1 xx m ute channel 3 xx1 xxx mute channel 4 x1 xxxx m ute channel 5 1 xxxxx m ute channel 6
rev. 0 ad1833a ?3 mclk select the ad1833a allows the matching of available external mclk frequencies to the required internal mclk rate. the mclk modification factor can be selected from 2, 1, or 2 / 3 by writing to bit 4 and bit 3 of control register 3. internally, the ad1833a requires an mclk of 24.576 mhz for sample rates of 48 khz, 96 khz, and 192 khz. in the case of 48 khz data with an mclk of 256 f s , a clock doubler is used, whereas with an mclk of 768 f s , a divide-by-3 block ( 3) is first implemented followed by a clock doubler. with an mclk of 512 f s , the mclk is passed through unmodified (see table xii). table xii. mclk settings bit 4 bit 3 modification factor 00 mclk 2 internally 01 mclk 1 internally 10 mclk 2 / 3 internally 11 reserved channel zero status the ad1833a provides individual logic output status indicators when zero data is sent to a channel for 1024 or more consecutive sample periods in all modes except right-justified. there is also table xiv. mclk vs. sample rate selection sampling rate interpolator mode internal mclk suitable external mclk frequencies (mhz) f s (khz) required required (mhz) mclk 2 mclk 1 mclk 2 / 3 32 8 64 4 16.384 8192 16.384 24.576 128 2 44.1 8 88.2 4 22.5792 11.2896 22.5792 33.8688 176.4 2 48 8 96 4 24.576 12.288 24.576 36.864 192 2 table xv. volume control registers address reserved * volume control 15?2 11 10 9? 00 10 00 channel 1 volume control (outl1) 00 11 channel 2 volume control (outr1) 01 00 channel 3 volume control (outl2) 01 01 channel 4 volume control (outr2) 01 10 channel 5 volume control (outl3) 01 11 channel 6 volume control (outr3) * must be programmed to zero. a global zero flag that indicates all channels contain zero data. the polarity of the zero signal is programmable by writing to control bit 2 (see table xiii). in right-justified mode, the six individual channel flags are best used as three stereo zero flags by combining pairs of them through suitable logic gates. then, w hen both the left and right inputs are zero for 1024 clock cycles, i.e., a stereo zero input for 1024 sample periods, the combined r esult of the two individual flags will become active, indicat- ing a stereo zero. table xiii. zero detect bit 2 channel zero status 0a ctive high 1a ctive low dac volume control registers the ad1833a has six volume control registers, one for each of the six dac channels. volume control is exercised by writing to the relevant register associated with each dac. this setting is used to attenuate the dac output. full-scale setting (all 1s) is equiv alent to zero attenuation (see table xv).
rev. 0 ad1833a ?4 i 2 s timing i 2 s timing uses an l /r clk to define when the data being trans- mitted is for the left channel and when it is for the right channel. the l /rclk is low for the left channel and high for the right channel. a bit clock running at 64 f s is used to clock in the data. there is a delay of 1 bit clock from the time the l /r clk signal changes state to the first bit of data on the sdinx lines. the data is written msb first and is valid on the rising edge of the bit clock. left-justified timing left-justified (lj) timing uses an l/ r clk to define when the data being transmitted is for the left channel and when it is for the right channel. the l/ r clk is high for the left channel and low for the right channel. a bit clock running at 64 f s is used left channel right channel lsb +1 lsb msb l /rclk input bclk input sdata input lsb +2 msb ? msb ? msb lsb +1 lsb lsb +2 msb ? msb ? msb figure 6. i 2 s timing diagram left channel right channel lsb +1 lsb l/rclk input bclk input sdata input lsb +2 msb ? msb ? msb lsb +1 lsb lsb +2 msb ? msb ? msb msb ? msb figure 7. left-justified timing diagram left channel right channel lsb +1 lsb l/ r clk input bclk input sdata input lsb +2 msb ? msb ? lsb msb lsb +1 lsb lsb +2 msb ? msb ? msb figure 8. right-justified timing diagram to clock in the data. the first bit of data appears on the sdinx lines when the l/ r clk toggles. the data is written msb first and is valid on the rising edge of the bit clock. right-justified timing right-justified (rj) timing uses an l/ r clk to define when the data being transmitted is for the left channel and when it is for the right channel. the l/ r clk is high for the left channel and low for the right channel. a bit clock running at 64 f s is used to clock in the data. the first bit of data appears on the sdinx 8-bit clock periods (for 24-bit data) after l/ r clk toggles. in rj mode, the lsb of data is always clocked by the last bit clock before l/ r clk transitions. the data is written msb first and is valid on the rising edge of the bit clock.
rev. 0 ad1833a ?5 tdm mode timing?nterfacing to a sharc in tdm mode, the ad1833a can be the master or slave, depend- ing on bit 0 in control register 3. in master mode, it generates a frame sync signal (fstdm) on its l/rclk pin and a bit clock (bclktdm) on its bclk pin, whereas in slave mode it expects these signals to be provided. these signals are used to control the data transmission from the sharc. the bit clock must run at a frequency of imclk/2 and the interpolation mode must be set to 8 , which limits tdm mode to frequencies of 48 khz or less. in this mode, all data is written on the rising edge of the bit clock and read on the falling edge of the bit clock. the frame starts with a frame sync at the rising edge of the bit clock. the sharc then starts outputting data on the next rising edge of the bit clock. each channel is given a 32-bit clock slot, and the data is left-justified and uses 16, 20, or 24 of the 32 bits. an enlarged diagram detailing this is provided (see figure 9). the data is sent from the sharc to the ad1833a on the sdin1 pin and provided in the following order: msb first?nternal dacl0, internal dacl1, internal dacl2, aux dacl0, internal dacr0, internal dacr1, internal dacr2, and aux dacr0. the data is written on the rising edge of the bit clock and read by the ad1833a on the falling edge of the bit clock. the left and right data destined for the auxiliary dac is sent in standard i 2 s format in the next frame using the sdin2, sdin3, and sout pins as the l/rclk, bclk, and sdata pins, respectively, for communicating with the auxiliary dac. dsp mode timing dsp mode timing uses the rising edge of the frame sync signal on the l/rclk pin to denote the start of the transmission of a data-word. note that for both left and right channels, a rising edge is used; therefore in this mode, there is no way to determine which data is intended for the left channel and which is intended for the right. the dsp writes data on the rising edge of bclk and the ad1833a reads it on the falling edge. the dsp raises the frame sync signal on the rising edge of bclk and then proceeds to transmit data, msb first, on the next rising edge of bclk. the data length can be 16, 20, or 24 bits. the frame sync signal can be brought low any time at or after the msb is transmitted, but must be brought low at least one bclk period before the start of the next channel transmission. internal dac l0 internal dac l1 internal dac l2 auxiliary dac l0 internal dac r0 internal dac r1 internal dac r2 auxiliary dac r0 fstdm bclktdm msb 24- bit data 20- bit data 16- bit data bclktdm msb ? msb ? msb ? msb ? lsb +8 lsb +7 lsb +6 lsb +5 lsb +4 lsb +3 lsb +2 lsb +1 lsb msb msb ? msb ? msb ? msb ? lsb +4 lsb +3 lsb +2 lsb +1 lsb msb msb ? msb ? msb ? msb ? lsb figure 9. tdm mode timing l/rclk bclk sdata msb msb ? msb ? msb ? msb ? msb ? msb msb ? msb ? msb ? msb ? msb ? msb ? msb 32 bclks 32 bclks msb ? figure 10. dsp mode timing
rev. 0 ad1833a ?6 packed mode 128 in packed mode 128, all six data channels are packed into one sample interval on one data pin. the bclk runs at 128 f s ; therefore, there are 128 bclk periods in each sample interval. each sample interval is broken into eight time slots: six slots of 20 bclk and two of 4 bclk. in this mode, the data length is restricted to a maximum of 20 bits. the three left channels are written first, msb first, and the data is written on the falling edge of bclk. after the three left channels are written, there is a space of four bclk, and then the three right channels are writ- ten. the l/ r clk defines the left and right data transmission; it is high for the three left channels and low for the three right channels. packed mode 256 in packed mode 256, all six data channels are packed into one sample interval on one data pin. the bclk runs at 256 f s ; therefore, there are 256 bclk periods in each sample interval, and each sample interval is broken into eight time slots of 32 bclk each. the data length can be 16, 20, or 24 bits. the three left channels are written first, msb first, and the data is written on the falling edge of bclk with a one bclk period delay from the start of the slot. after the three left channels are written, there is a space of 32 bclk, and then the three right channels are written. the l /rclk defines the left and right data transmission; it is low for the three left channels and high for the three right channels. slot 1 left 0 slot 2 left 1 slot 3 left 2 blank slot 4 sclk slot 4 right 0 slot 5 right 1 slot 6 right 2 blank slot 4 sclk data 20-bit data 16-bit data bclk bclk msb ? msb ? msb ? msb ? msb ? msb ? msb ? msb ? lsb +4 lsb +3 lsb +2 lsb +1 msb lsb lsb msb l/ r clk figure 11. packed mode 128 slot 1 left 0 slot 2 left 1 slot 3 left 2 slot 4 right 0 slot 5 right 1 slot 6 right 2 20-bit data 24-bit data 16-bit data bclk msb ? msb ? msb ? msb ? msb ? msb ? msb ? msb ? lsb +8 lsb +7 lsb +6 lsb +5 lsb +4 lsb +3 lsb +2 lsb +1 lsb +4 lsb +3 lsb +2 lsb +1 msb lsb lsb lsb msb msb ? msb ? msb ? msb ? msb data bclk l /rclk figure 12. packed mode 256
rev. 0 ad1833a ?7 20 40 60 80 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 100 120 khz dbr 0 figure 16. dynamic range for 37 khz @ ?0 dbfs, 110 db, triangular dithered input 20 40 60 80 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 100 120 khz dbr 0 figure 17. input 0 dbfs @ 37 khz, bw 20 hz to 120 khz, sr 96 khz, thd + n ?5 dbfs 2468 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 10 12 khz dbv 0 ?60 14 16 18 20 figure 18. noise floor for zero input, sr 48 khz, snr 110 dbfs a-weighted 3.81k 270pf npo 11k 68pf npo 11k v out 5.62k v out+ 560pf npo 1.50k 5.62k 150pf npo op275 604 2.2nf npo vfilt out 5 6 7 100pf npo figure 13. suggested output filter schematic 246810 12 14 16 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 18 20 khz dbr 0 figure 14. dynamic range for 1 khz @ ?0 dbfs, 110 db, triangular dithered input 246810 12 14 16 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 18 20 khz dbr 0 figure 15. input 0 dbfs @ 1 khz, bw 20 hz to 20 khz, sr 48 khz, thd + n ?5 dbfs
rev. 0 ad1833a ?8 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 dbfs dbr ?00 ?00 ?0 ?0 ?0 0 ?0 ?10 ?20 figure 20. thd + n ratio vs. input amplitude, input 1 khz, sr 48 khz, 24-bit ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?0 ?0 dbfs dbr ?00 ?0 ?0 ?0 0 ?0 ?10 ?20 figure 19. thd + n amplitude vs. input amplitude, input 1 khz, sr 48 khz, 24-bit
rev. 0 ad1833a ?9 clatch cdata cclk l/rclk bclk sdin1 sdin2 sdin3 sout mclk outlp1 outln1 outlp2 outln2 outlp3 outln3 outrp1 outrn1 outrp2 outrn2 outrp3 outrn3 filtr filtd dgnd1 dgnd2 gnd dv dd1 dv dd2 av dd1 av dd2 av dd av dd av dd ad1833a 0.1 f + + + 0.1 f 10 f 0.1 f 10 f 0.1 f 10 f av dd 5v 5v + + 0.1 f 10 f 0.1 f 10 f 0.1 f 10 f 0.1 f 10 f + + clatch cdata cclk l1+ l1 l2+ l2 l3+ l3 r1+ r1 r2+ r2 r3+ r3 1 2 47 48 45 46 36 35 38 37 40 39 42 43 14 15 16 17 18 20 21 22 23 19 gnd gnd gnd gnd gnd gnd + 10 f 0.1 f + 10 f rxp rxn filt agnd dgnd sdata fsync sck mck m0 m1 m2 m3 c u cbl verf erf co/eo ca/e1 cb/e2 cc/f0 cd/f1 ce/f2 sel cs12/fck dir-cs8414 shld1 shld1 shld1 shld1 dv dd out u5 torx173 10nf 10nf 47nf 1k 75ro 5v 10k 0.1 f l5 0.1 f 10 f 26 11 12 19 23 24 18 17 1 14 15 28 25 6 5 4 3 2 27 16 13 8 21 20 10 9 va+ vd+ 5 6 2 4 1 pal dv dd av dd 730 631 53241 29 8 3 dv dd ?ntf 22 7 928 433 33444 figure 21. example digital interface
rev. 0 c02336??/03(0) ad1833a ?0 outline dimensions 48-lead low profile quad flat package [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane

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